The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to a semiconductor structure with improved gate planarity and a method of forming the same.
In an effort to build integrated circuits with higher performance and increased yields, a number of process technologies have emerged. One such technology improvement is to use a sacrificial gate structure to improve the geometry, manufacturability and performance of a gate structure.
In a typical replacement metal gate process, also known as a gate-last process, a sacrificial gate material (e.g., polysilicon) is used for forming a self-aligned gate-to-source/drain structure. Subsequently, the sacrificial gate material is removed and replaced with a gate structure including desired gate dielectrics and gate electrode. In the gate-last process, gate height control is critical to proper transistor function since variation in gate height may lead to measurable transistor performance variability.
In the gate-last process, Chemical Mechanical Polishing (CMP) is used to expose the sacrificial gate structure for subsequent removal and it is also used to remove excess final gate fill metal after the replacement gate structure is finished. The CMP process requires extreme control over final gate height and topography. However, problems arise when integrating the gate-last process with CMP processes because it may be difficult to control a uniform gate height for devices in various regions of the substrate having different pattern densities during the CMP processes.
Therefore, there remains a need to provide a field effect transistor (FET) with improved gate planarity in a replacement metal gate process.